The present invention generally relates to semiconductor devices and more particularly to a high-voltage MOS device having a so-called semiconductor-on-insulator or SOI structure.
In the SOI structure, active devices are constructed on respective insulator layers which in turn are provided on a semiconductor substrate. By using this structure, complete device isolation is achieved. Thus, there are various attempts to construct high-voltage MOSFETs, such as the one used in the display panel driving or in the electro-mechanical control where a high withstand voltage is required, in a form of the SOI structure.
FIG. 1 shows a prior art MOSFET device having such an SOI structure. The MOSFET shown in the drawing has a so-called offset gate structure wherein the source and drain regions of the device are provided asymmetrically with respect to the gate, and the gate is provided close to the source region of the device.
Referring to FIG. 1, this prior art MOSFET device comprises a silicon substrate 11 of a first conductive type, an insulator layer 12 typically of sapphire and provided on the substrate 11, and a semiconductor layer 13 on the insulator layer 12. The semiconductor layer 13 is doped to the first conductive type and is covered by a gate insulator film 14 in correspondence to a part of the semiconductor layer 13 where a gate electrode 15 is provided, and the gate electrode 15 is provided on the gate insulator film 14 as usual. Further, a source region 17 and a drain region 18, both having a second conductive type, are defined in the semiconductor layer 13 with such a relation that the source region 17 is located adjacent to the gate electrode 15 while the drain region 18 is separated from the gate electrode 15 by an offset region 19. This offset region 19 includes a less-doped region 19a in the upper part thereof. This region 19a is doped to the second conductive type though with a reduced dopant level.
The active part of the MOSFET of FIG. 1 is thus formed on the semiconductor layer 13 which is isolated from other MOSFET devices on the same substrate. Thus, an ideal device isolation is achieved when the MOSFET is assembled in a form of integrated circuit.
Such a MOSFET having the offset gate structure provides a preferable feature in that the drain breakdown voltage is increased by reducing the thickness of the semiconductor layer 13. More specifically, when the thickness of the semiconductor layer 13 is reduced, the offset region 19 is depleted substantially entirely in response to the drain voltage because of the reverse biasing of a p-n junction formed in this offset region between the less-doped region 19a and the rest of the semiconductor layer 13 underneath. Note that the less-doped region 19a has the second conductive type while the semiconductor layer 13 in the region 19 has the first conductive type. Thus, when the drain voltage is applied between the source and drain regions, the depletion region spreads upwards and downwards in the vertical direction from the p-n junction in the offset region. With reduced thickness of the offset region 19, the depletion region formed therein easily extends throughout its entire thickness. In such a situation, increase of the drain voltage contributes only to the increase of lateral electric field across the offset region. Therefore, the expansion of the offset length makes the drain breakdown voltage higher.
In the MOSFET having the offset gate structure as such, however, there arises a problem in that the resistance between the source region 17 and the drain region 18 in the turn-on state of the device or so-called on-resistance is increased because of the existence of depletion region in the offset region 19. In order to reduce this on-resistance, it is necessary that the dose of the less-doped region 19 including the less-doped region 19a is increased. However, increase of the dose in the region 19 raises a problem in that the impurities tend to be diffused into the region underneath the less-doped region 19a upon heat treatment applied during the fabrication process. Thus, it is difficult to limit the less-doped region 19a in the upper part of the semiconductor layer 13 when the dose is increased.
Further, because of the tendency of non-uniform distribution of the electric field in the semiconductor layer 13, there appears a concentration of an electric field in the source side edge of the doped regions 19a and 18 shown in FIG. 1 by A and B. As the p-n junction is formed in the region A or B, the excessive increase of the electric field in such a region invites a breakdown of the junction when the dose is increased in the region 19. Thus, the drain breakdown voltage, which is substantially determined by the regions A and B, is deteriorated and the device becomes fragile to the surge of the drain voltage.
From the foregoing reasons, the approach to increase the dose of the impurities is inappropriate, and the problem of achieving a high drain breakdown voltage and at the same time a reduced on-resistance remains unsolved.